Invention relates to amplifier circuits, and more particularly to switching amplifier power switch.
xe2x80x9cTypical Class-D amplifier such as that of Texas Instrument (TI) Cass D Stereo Audio Power Amplifier described in TI TPA005D02 Class D Stereo Audio Power Amplifier Evaluation Module User""s Guide comprises an analog input and an analog output. A simplified Class-D amplifier is illustrated in FIG. 1. The amplifier constitutes two parts: the control circuit 20 and the H-bridge 30. The control circuit 20 consists of a saw-tooth waveform generator 201 and a comparator 202. The analog input 11 is compared with the saw-tooth waveform to produce a binary digital output 31. The binary digital output is then used to control the ON/OFF of an output power stage such as an H-bridge circuit 30. As shown in greater detail in FIG. 2, H-bridge circuit 30 comprises two pairs of switches, a first pair of switches: switch 102 (AH) and switch 104 (AL), and a second pair of switches: switch 106 (BH) and 108 (BL). Each pair of switches comprises a first switch (i.e., AH or BH) connected to a positive power supply 101 (VP) and a second switch (i.e., AL or BL) that is connected to a negative power supply 103 (VM) to thereby switch amplifier 20 between a positive and negative digital output state (i.e., equivalent to a digital xe2x80x9c+1xe2x80x9d output voltage and a xe2x80x9cxe2x88x921xe2x80x9d output voltage) via a set of input switch control signals 105, 107, 109, and 111 (VAH, VAL, VBH, and VBL, respectively). The output load 110 is connected to the output switches via the output nodes 112 (V+) and 114 (Vxe2x88x92) as shown in FIG. 2. During the xe2x80x9c+1xe2x80x9d state, the set of amplifier switch control signals 105, 107, 109, and 111 controlling switches, AH, AL, BH, and BL are designed to connect node 112 (V+) to positive power supply (VP) and node 114 (Vxe2x88x92) to negative power supply (VM). During the xe2x80x9cxe2x88x921xe2x80x9d state, the set of amplifier switch control signals 105, 107, 109, and 111 controlling switches, AH, AL, BH, and BL are designed to connect node 112 (V+) to negative power supply (VM) and node 114 (Vxe2x88x92) to positive power supply (VP). For traditional Class-D amplifier, the output switches between xe2x80x9c+1xe2x80x9d and xe2x80x9cxe2x88x921xe2x80x9d states alternatively depends on the control circuit 20. Depending upon the nature of the input waveform, the switch-on time for the pull-up and pull-down transistors can be very narrow such that the pulse is shorter or comparable to the rise time or fall time of the power switches 105, 107, 109, 111. This correspondingly also results in distortion in the output circuit. In real implementations, special transistors (e.g., DMOS or JFET) are used in the H-bridge since they have much faster turn-on time that a standard MOS transistor. An apparent drawback for this type of Class-D amplifier is that while the control circuit 20 in FIG. 1 can be implemented in CMOS, the H-bridge is typically outside the controller circuit. Since modern VLSI adapts CMOS as the dominant technology due to its advantage of lower cost and high integration capability. The integration level is not optimum and hence the cost is higher than a single integrated CMOS Class-D amplifier.xe2x80x9d
Another prior solution, such as shown in U.S. Pat. No. 5,777,512 (xe2x80x9cthe ""512 Patentxe2x80x9d), includes a feedback loop to reduce the overall harmonic distortion of the H-bridge. In the ""512 Patent, an analog sigma-delta modulator is used to produce the binary digital output, and the output of the amplifier is then fed back to the sigma-delta loop to reduce the distortion. Both the traditional saw-tooth and binary sigma-delta modulation provide poor power efficiency due to their frequent switching even when there are little or no input signals. Another problem is caused by the binary nature of the output state and finite turn-on resistance associated with the transistors of the H-bridge is that there will always be power consumed by these transistors regardless of the shape or amplitude of the input signal. As illustrated in FIG. 2, due to the binary nature of the output state, at any given time, either the transistor 102 and 108 are xe2x80x9cONxe2x80x9d (+1 state), or 106 and 104 are xe2x80x9cONxe2x80x9d (xe2x88x921 state). In either case, there is a current path from positive supply 101 to negative power supply 103. The power consumed by each transistor 102, 104, 106, and 108 is the product of the current times the turn-on resistance associated with each transistor. Thus, because of these binary states, power consumption is always present even if there is no input signal to amplify.
xe2x80x9cIn U.S. Pat. No. 5,077,539 (xe2x80x9cthe ""539 Patent), a ternary output switching amplifier is introduced. A major advantage of the ternary output switching amplifier is the higher power efficiency for small input signal. This efficiency is achieved by introducing the third state 0. In FIG. 2, when the amplifier outputs a 0 state, both output terminals 112 (V+) and 114 (Vxe2x88x92) of output load 110 are short circuited to a supply voltage of a pre-determined polarity, i.e., the positive power supply voltage. Since both the output terminals have the same voltage, there is no current flow through the load and the transistors 102, 104, 106, and 108, hence the power consumption is zero during 0 state. If designed properly, for a small amplitude input signal, the output preferably will have many 0 states and the power consumption is then much smaller than the binary switching amplifiers described earlier. One possible implementation of ternary switching amplifier is disclosed in U.S. Pat. No. 5,617,058 (xe2x80x9cthe ""058 Patentxe2x80x9d), in which a pulse width logic is used to convert digital data into a ternary switching signal. While the ternary power switch amplifier can achieve higher power efficiency than binary power switch amplifiers, there is significant harmonic distortion caused by the error caused by the error voltages associated with the output transistors as explained below:xe2x80x9d
As illustrated in FIG. 5, there are error voltages associated with the output nodes V+ and Vxe2x88x92 switching between the positive and negative supply voltages. The associated error voltages result from the finite rise and fall time as well as the settling time of the output transistors 102, 104, 106, and 108. The error voltages associated with these transistors are correspondingly denoted as V(AH), V(AL), V(BH) and V(BL). To simply the analysis, we assume that error occurs when the transistors change from xe2x80x9cOffxe2x80x9d (opened) to xe2x80x9cONxe2x80x9d (closed). Since the turn-off time of a transistor is independent of the load and can be well controlled, it is typically much shorter than the turn-on time. Thus, the error associated with the turn-off time of a transistor is much shorter than that associated with the turn-on time of a transistor. We therefore neglect its effect in the following analysis. In the preferred typical implementation, the transistors 102 and 106 are of the same type (for example PMOS) and transistors 104 and 108 are of the same type (for example NMOS) and are operated under the same switching condition. Thus, V(AH)=V(BH), and V(AL)=V(BL). On the other hand, the pull-up transistors 102 and 106, and the pull-down transistors 104 and 108 are typically of different type or switched under different conditions. Hence, these transistors are not matched, and consequently V(AL)xe2x89xa0V(AH) and V(BL)xe2x89xa0V(BH). Accordingly, due to this mismatch, the ternary switching sequence introduces substantial harmonic distortion at the output.
For example, consider the switching sequence shown in FIG. 4 wherein the output switches between just the +1 state and the 0 state. At each occurrence of a 0 state, both nodes V+ and Vxe2x88x92 of load 110 are typically switched xe2x80x9cHIGHxe2x80x9d to supply VP (referring to FIG. 2). As seen from FIG. 4, the positive end of the load (V+) always remain at VP, while the negative end of the load (Vxe2x88x92) switches to VP at each occurrence of a 0 state. Input switch control signals are designed to alternately switch BH and BL close. Since the rise time and fall time of switches BH and BL do not typically match, the harmonic distortion is increased from the switching operation. From another perspective, for ternary and xe2x80x9creturn-to-zeroxe2x80x9d switching amplifier, there are only two kinds of state transition between two 0 states. These state transitions are:
1. 0xe2x86x92+1xe2x86x920
2. 0xe2x86x92xe2x88x921xe2x86x920
As illustrated in FIG. 2, during a 0 state, i.e., both V+ and Vxe2x88x92 are at the positive supply VP, hence transistors 102 and 106 are closed while transistors 104 and 108 are open as shown in Table 1.
For 0xe2x86x921 transition, the transistor BL switches from opened to closed. The error voltage associated with this operation is xe2x88x92V(BL). The minus sign accounts for the fact that switch BL connects to the negative output Vxe2x88x92. For 1xe2x86x920 transition, BH changes from opened to closed. The error voltage associated with this operation is V(BH). The total error voltage for this 0xe2x86x921xe2x86x920 transition is therefore xe2x88x92V(BL) +V(BH). As explained earlier, transistors BL and BH do not match, and hence there is a residual error voltage associated with this transition. Similarly, for the transition 0xe2x86x921xe2x86x920, this residual error voltage buildup also applies to produce a residual error voltage corresponding to V(AL)xe2x88x92V(AH). The error voltages associated with these two transition types are summarized in TABLE 2.
Since the occurrence for these two types of transition 0xe2x86x921xe2x86x920 and 0xe2x86x92xe2x88x921xe2x86x920 depend on the input signal, the residual voltages causes overall harmonic distortion and noise of the output. In addition, if there is a (1 to xe2x88x921) or (xe2x88x921 to 1) transition as illustrated in FIG. 3, the combined error voltage is further compounded for turning two output switches from OFF to ON at the same time. There is therefore a need for an improved switching amplifier circuit that minimizes residual error voltage, the harmonic distortion, as well as noise output during switching operations.
Invention resides in a switching amplifier comprising amplifier input control signals that generate four digital output levels (1, 0H, 0L, xe2x88x921). The control signals input are designed to generate an alternating zero output states, alternating from a zero state at a High level 0H to a zero state at a Low level 0L between each non-zero state. The 0H state comprises short circuiting a load of the amplifier to a positive voltage VP, the 0L comprises short circuiting the load to the negative voltage supply VM, and the xe2x80x9cnon-zero statexe2x80x9d being either a positive (+1) or a negative (xe2x88x921) output state. With an alternating zero output state between each positive (+1) and negative (xe2x88x921) output state, error voltage cancellation is achieved to thereby minimize the error voltage and associated harmonic distortion and noise associated at the output of the switching amplifier during switching operations.